High-speed Sensing Scheme for CMOS DRAM's

Sang H. Dhong, Nicky Chau Chun Lu, Wei Hwang, Stephen A. Parke

Research output: Contribution to journalArticle

15 Scopus citations


A new sensing scheme for CMOS DRAM's is introduced and discussed. A significant improvement in sensing speed over the half-VDD bitline precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 VDD. The 2/3-VDD sensing scheme also results in higher bitline capacitance, asymmetrical bitline swing, and higher power consumption. However, the speed advantage of 2/3-VDD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted wordline case, symmetrical bitline swing can be retained by limiting the bitline downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. This detailed study shows that the 2/3-VDD sensing with a limited bitline swing has several unique advantages over the half-VDD sensing scheme such as a faster signal development time, reduced power consumption, and smaller noise. Also, it is particularly suitable for highperformance highdensity CMOS DRAM's, where boosting the wordlines is difficult to achieve because of device reliability concerns in the scaled-down devices.

Original languageEnglish
Pages (from-to)34-40
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - 1 Feb 1988

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