High Speed Negative Capacitance Ferroelectric Memory

Chun-Yen Chang; Chia Chi Fan; Chien Liu; Yu Chien Chiu; Chun-Hu Cheng

doi:10.1109/ASICON.2017.8252397

High Speed Negative Capacitance Ferroelectric Memory

Chun-Yen Chang, Chia Chi Fan, Chien Liu, Yu Chien Chiu, Chun-Hu Cheng

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.

Original language	English
Title of host publication	12th IEEE International Conference on ASIC (ASICON)
DOIs	https://doi.org/10.1109/ASICON.2017.8252397
State	Published - 2017

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Chang, C-Y., Fan, C. C., Liu, C., Chiu, Y. C., & Cheng, C-H. (2017). High Speed Negative Capacitance Ferroelectric Memory. In 12th IEEE International Conference on ASIC (ASICON) https://doi.org/10.1109/ASICON.2017.8252397

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title = "High Speed Negative Capacitance Ferroelectric Memory",

abstract = "This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.",

author = "Chun-Yen Chang and Fan, {Chia Chi} and Chien Liu and Chiu, {Yu Chien} and Chun-Hu Cheng",

year = "2017",

doi = "10.1109/ASICON.2017.8252397",

language = "English",

isbn = "978-1-5090-6625-4",

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AU - Fan, Chia Chi

AU - Liu, Chien

AU - Chiu, Yu Chien

AU - Cheng, Chun-Hu

PY - 2017

Y1 - 2017

N2 - This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.

AB - This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.

U2 - 10.1109/ASICON.2017.8252397

DO - 10.1109/ASICON.2017.8252397

M3 - Conference contribution

SN - 978-1-5090-6625-4

BT - 12th IEEE International Conference on ASIC (ASICON)

ER -