High-Speed Median Filter Designs Using Shiftable Content-Addressable Memory

Chen-Yi Lee, Po Wen Hsieh, Jer Min Tsai

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many image/video applications. The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs. To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture. The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells— sort-cell and compare-cell. Thus the design becomes very regular. More specifically any specified order can be obtained within one cycle and a high-speed clock rate can be achieved. A proto-type chip for 64 samples based on this architecture has been implemented and tested. Results show that a clock rate up to 50 MHz can be achieved using a 1.2 pm CMOS double metal technology.

Original languageEnglish
Pages (from-to)544-549
Number of pages6
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume4
Issue number6
DOIs
StatePublished - 1 Jan 1994

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