High speed, high linearity CMOS buffer amplifier

Trond Sæther*, Chung-Chih Hung, Zheng Qi, Mohammed Ismail, Oddvar Aaserud

*Corresponding author for this work

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 μm double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A o = 70 dB, GBW = 5.5 MHz, SR = 7 V/μs, and υ n = 10nV/√Hz@100 kHz. With a supply voltage of ±5 V, the amplifier has a ±4.7 V output swing and features a low 30 Ω open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V out,pp output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.

Original languageEnglish
Pages (from-to)255-258
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume31
Issue number2
DOIs
StatePublished - 1 Feb 1996

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