High-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

Joseph D. George*, Jerome D. Harr, Rock Young, Gerry T. Watanabe, Carl J. Anderson, Young H. Kwark, Harris F. Basit, Shushau Fang, Keh chung Wang, Peter M. Asbeck, Mau-Chung Chang, Randy Nubling, Gerald J. Sullivan, Mark McDonald, Chuck Honaker, Tom McDermott

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have ft values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.

Original languageEnglish
Pages (from-to)186-187, 336
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume32
DOIs
StatePublished - 1 Dec 1989
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 15 Feb 198917 Feb 1989

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