High-Speed GaAs Frequency Dividers Using a Self-Aligned Dual-Level Double Lift-Off Substitution Gate MESFET Process

Mau-Chung Chang, S. J. Lee, E. R. Walton, C. P. Lee, F. J. Ryan, R. P. Vahrenkamp, K. Kirkpatrick

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

A new self-aligned substitution gate process, which uses a dual-level resist (photoresist/polymethylmethacrylate (PMMA)) and a double lift-off technique has been successfully developed for the fabrication of MESFET circuits on 3-in GaAs wafers. Good device uniformity (20-mV standard deviation of threshold voltage) and excellent device characteristics (gm= 280 mS/mm) were obtained. Single-clocked divide-by-four frequency dividers with direct-coupled FET logic (DCFL) and five-gate delay design were fabricated by the above process. The maximum input frequency measured was 4.4 GHz. The minimum power dissipation was a 0.55-mW/gate with a speed-power product of 39 fJ.

Original languageEnglish
Pages (from-to)279-281
Number of pages3
JournalIEEE Electron Device Letters
Volume6
Issue number6
DOIs
StatePublished - 1 Jan 1985

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