High-speed digital comb filter for ΣΔ analog-to-digital conversion

Louis Luh*, John Choma, Jeffrey Draper, Her-Ming Chiueh

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

5 Scopus citations

Abstract

A new approach for implementing a digital decimator for high-speed ΣΔ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2μm standard CMOS process. With a single 5V power supply, this filter can operate at a frequency up to 115MHz. The power consumption is about 35mW and the active area is 1083 × 965 μm2.

Original languageEnglish
Pages356-359
Number of pages4
StatePublished - 1 Dec 1999
Event1999 IEEE 42nd Midwest Symposium on Circuits and Sistems - Las Cruces, NM, USA
Duration: 8 Aug 199911 Aug 1999

Conference

Conference1999 IEEE 42nd Midwest Symposium on Circuits and Sistems
CityLas Cruces, NM, USA
Period8/08/9911/08/99

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