High-speed CMOS current-mode wave-pipelined analog-to-digital converter

Chung-Yu Wu*, Yu Yee Liow

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, a new architecture 8-bit CMOS wave- pipelined current-mode A/D converter (IADC) is proposed and analyzed. The wave-pipelined theory is applied to the structure of the IADC. Thus, the conventional current sample-and-hold circuit is not needed in each stage of the pipelined IADC. From the HSPICE simulation results, the proposed IADC can achieve 8-bit accuracy with a sampling rate up to 20MS/s when the input signal frequency is 900KHz. The power dissipation of the IADC is 450mW at 20MS/s of conversion rate with a single 5V power supply. The proposed IADC is designed and fabricated in a double-poly quadruple-metal 0.35μm CMOS process.

Original languageEnglish
Title of host publicationICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages907-910
Number of pages4
DOIs
StatePublished - 1 Dec 2000
Event7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon
Duration: 17 Dec 200020 Dec 2000

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2

Conference

Conference7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
CountryLebanon
CityJounieh
Period17/12/0020/12/00

Fingerprint Dive into the research topics of 'High-speed CMOS current-mode wave-pipelined analog-to-digital converter'. Together they form a unique fingerprint.

Cite this