High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer

Hung Bin Chen, Yung Chun Wu, Lun-Chun Chen, Ji-Hong Chiang, Chao-Kan Yang, Chun-Yen Chang

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.
Original languageEnglish
Pages (from-to)537-539
Number of pages3
JournalIEEE Electron Device Letters
Volume33
Issue number4
DOIs
StatePublished - Apr 2012

Keywords

  • Nanocrystal (NC); nonvolatile memory (NVM); thin-film transistor (TFT)
  • SILICON; GATE; SONOS

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