High power-added efficiency and low distortion GaAs power FET employing spike-gate structure

Hidetoshi Furukawa*, Tsuyoshi Tanaka, Hiroshi Takenaka, Tetsuzo Ueda, Takeshi Fukui, Daisuke Ueda

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A GaAs power FET employing a spike-gate structure was developed for the high efficiency and low distortion operation under the extremely low supply voltage of 1.5 V. This spike-gate FET is featured by an unique gate structure that has almost zero effective gate length. The spike-gate provides both the low on-resistance of 2.2 Ω mm -1 and the low drain conductance of 5 mS mm -1 . Maximum frequency of oscillation (f max ) is over 30 GHz that is estimated from S-parameter under the supply voltage of 1.5 V. The decrease of the f max is smaller for the spike-ate FET than for the conventional one as the decrease of supply voltage. In π/4-shift QPSK modulation system, the implemented device achieved the output power of 31.0 dBM with 52% power-added efficiency and -51 dBc adjacent channel leakage power at the frequency of 925 MHz under the drain supply voltage of 1.5 V.

Original languageEnglish
Pages (from-to)1599-1604
Number of pages6
JournalSolid-State Electronics
Volume41
Issue number10
DOIs
StatePublished - 1 Jan 1997

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