High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

P. J. Sung, T. C. Cho, P. C. Chen, F. J. Hou, C. H. Lai, Y. J. Lee, Y. Li, S. Samukawa, T. S. Chao, W. F. Wu, W. K. Yeh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, strain effects on silicon n-channel gate-all-around (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (Ion/Ioff >109) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.

Original languageEnglish
Title of host publication16th International Conference on Nanotechnology - IEEE NANO 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages174-175
Number of pages2
ISBN (Electronic)9781509039142
DOIs
StatePublished - 21 Nov 2016
Event16th IEEE International Conference on Nanotechnology - IEEE NANO 2016 - Sendai, Japan
Duration: 22 Aug 201625 Aug 2016

Publication series

Name16th International Conference on Nanotechnology - IEEE NANO 2016

Conference

Conference16th IEEE International Conference on Nanotechnology - IEEE NANO 2016
CountryJapan
CitySendai
Period22/08/1625/08/16

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