High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

Horng-Chih Lin*, Meng Fan Wang, Fu Ju Hou, Hong Nien Lin, Chia Yu Lu, Jan Tsai Liu, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

29 Scopus citations

Abstract

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.

Original languageEnglish
Pages (from-to)102-104
Number of pages3
JournalIEEE Electron Device Letters
Volume24
Issue number2
DOIs
StatePublished - 1 Feb 2003

Keywords

  • Ambipolar
  • Schottky barrier
  • Silicon-on-insulator (SOI)

Fingerprint Dive into the research topics of 'High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions'. Together they form a unique fingerprint.

Cite this