High performance of Ge nMOSFETs Using SiO2 interfacial layer and TiLaO gate dielectric

W. B. Chen, Albert Chin

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


Using a SiO2 interfacial layer and a high- κ gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm2(V.s)at 0.5 MV/cm, and a very low off-state leakage current of 3.5×10-10 A/μ. The self-aligned and gate-first metal-gate/high- κ and Ge nMOSFETs were processed using standard ion implantation and 550 °C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.

Original languageEnglish
Article number5345768
Pages (from-to)80-82
Number of pages3
JournalIEEE Electron Device Letters
Issue number1
StatePublished - 1 Jan 2010


  • Ge
  • TaN
  • TiLaO

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