High performance n+/p junction technology for high mobility Ge nMOSFET

Albert Chin, Shih Han Yi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (Ev). It is also hard to form n+/p Ge junction by standard ion implantation due to the poor dopant activation by rapid thermal annealing (RTA) and fast impurity diffusion. Here high performance metal-gate/high-k/(111)-Ge nMOSFET was achieved with good 1.05 junction ideality factor (n), large 5 orders on/off junction current, and higher mobility than SiO2/Si data at wide range carrier density (Ns) at small 0.85 nm equivalent-oxide thickness (EOT). The excellent n+/p Ge junction is attributed to the fast 30-ns laser annealing (LA) and YbGe2-x/n-Ge contact with less Fermi-level pinning.

Original languageEnglish
Title of host publication2014 International Workshop on Junction Technology, IWJT 2014
PublisherIEEE Computer Society
Pages140-143
Number of pages4
ISBN (Print)9781479936274
DOIs
StatePublished - 1 Jan 2014
Event14th International Workshop on Junction Technology, IWJT 2014 - Shanghai, China
Duration: 18 May 201420 May 2014

Publication series

Name2014 International Workshop on Junction Technology, IWJT 2014

Conference

Conference14th International Workshop on Junction Technology, IWJT 2014
CountryChina
CityShanghai
Period18/05/1420/05/14

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  • Cite this

    Chin, A., & Yi, S. H. (2014). High performance n+/p junction technology for high mobility Ge nMOSFET. In 2014 International Workshop on Junction Technology, IWJT 2014 (pp. 140-143). [6842048] (2014 International Workshop on Junction Technology, IWJT 2014). IEEE Computer Society. https://doi.org/10.1109/IWJT.2014.6842048