High-performance GAA sidewall-damascened sub-10-nm in situ n+-doped poly-Si NWs channels junctionless FETs

Po Yi Kuo*, Yi Hsien Lu, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

The gate-all-around sidewall-damascened sub-10-nm in situ n+-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm2 cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (VTH) and subthreshold swing (S.S.) on dimension of in situ n+-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. ∼ 75 mV/decade; 2) low gate supply voltage (VG) = 1.5 V; 3) high ON/OFF currents ratio (ION/ IOFF) ∼ 8 × 107) and significantly high-thermal stability without implantation processes and hydrogen-related plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications.

Original languageEnglish
Article number6897955
Pages (from-to)3821-3826
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume61
Issue number11
DOIs
StatePublished - 1 Nov 2014

Keywords

  • Gate-all-around (GAA)
  • junctionless (JL)
  • sidewall-damascened nanowires (SWDNWs)

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