High performance design of tunneling FET for low voltage/power applications: Strategies and solutions

Steve S. Chung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. Two different approaches have been demonstrated. The first design is based on the design of a raised-drain structure which results in a low Cgd, and the reduction of source-to-drain leakage. The second design is based on the concept of alignment between the max. electric field and B2BT rate to enhance the performance of TFET. It was demonstrated in an L-gate structure TFET. Both cases show an efficient improvement of the Ion current, lower S.S. and good delay performance. Finally, a bi-directional pass gate has been applied to complementary TFET SRAM to improve the WNM and RSNM, with operation voltage down to 0.3V. This shows great potential of the proposed TFET structure and schemes for ultra-low power applications.

Original languageEnglish
Title of host publication7th IEEE International Nanoelectronics Conference 2016, INEC 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467389693
DOIs
StatePublished - 12 Oct 2016
Event7th IEEE International Nanoelectronics Conference, INEC 2016 - Chengdu, China
Duration: 9 May 201611 May 2016

Publication series

NameProceedings - International NanoElectronics Conference, INEC
Volume2016-October
ISSN (Print)2159-3523

Conference

Conference7th IEEE International Nanoelectronics Conference, INEC 2016
CountryChina
CityChengdu
Period9/05/1611/05/16

Keywords

  • Band-to-band tunneling
  • low power
  • SRAM
  • Tunneling FET

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