The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. Two different approaches have been demonstrated. The first design is based on the design of a raised-drain structure which results in a low Cgd, and the reduction of source-to-drain leakage. The second design is based on the concept of alignment between the max. electric field and B2BT rate to enhance the performance of TFET. It was demonstrated in an L-gate structure TFET. Both cases show an efficient improvement of the Ion current, lower S.S. and good delay performance. Finally, a bi-directional pass gate has been applied to complementary TFET SRAM to improve the WNM and RSNM, with operation voltage down to 0.3V. This shows great potential of the proposed TFET structure and schemes for ultra-low power applications.