High-performance deadlock-free ID assignment for advanced interconnect protocols

Hsuan Ming Chou, Yi Chiao Chen, Keng Hao Yang, Jean Tsao, Shih Chieh Chang, Wen Ben Jone, Tien-Fu Chen

Research output: Contribution to journalArticlepeer-review


In a modern system-on-chip design, hundreds of cores and intellectual properties can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols that support novel mechanisms of parallel accessing, including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to transaction deadlocks that do not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can incur serious performance penalty. In this brief, we propose a novel ID assignment mechanism that guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of transaction stalls issued by masters. Our experimental results show encouraging performance improvements compared with previous works with little hardware and power overheads.

Original languageEnglish
Article number7112547
Pages (from-to)1169-1173
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - 1 Mar 2016


  • Advanced interconnect protocol
  • Deadlock
  • System on chip (SoC)

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