High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding

Min C. Tsai; Tian-Sheuan Chang

doi:10.1109/APCCAS.2006.342056

High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding

Min C. Tsai^*, Tian-Sheuan Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

This paper presents a high-performance VLSI architecture for context adaptive variable length coding (CAVLC) used in the MPEG-4 AVC/H.264 video coding. Instead of only the coarse-grained 8×8 zero block skipping in the previous design, the proposed design implements the fine-grained zero skipping at the 4×4 block level and the individual coefficient level. The implementation with 0.18um CMOS process just needs average 6.88 cycles for one block coding and costs 11.9K gates when working at 100 MHz. This design saves more than half of cycle count and 48% of area cost when compared with the other designs.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	586-589
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342056
State	Published - 1 Dec 2006
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 4 Dec 2006 → 6 Dec 2006

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country	Singapore
Period	4/12/06 → 6/12/06

Access to Document

10.1109/APCCAS.2006.342056

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Cite this

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title = "High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding",

abstract = "This paper presents a high-performance VLSI architecture for context adaptive variable length coding (CAVLC) used in the MPEG-4 AVC/H.264 video coding. Instead of only the coarse-grained 8×8 zero block skipping in the previous design, the proposed design implements the fine-grained zero skipping at the 4×4 block level and the individual coefficient level. The implementation with 0.18um CMOS process just needs average 6.88 cycles for one block coding and costs 11.9K gates when working at 100 MHz. This design saves more than half of cycle count and 48% of area cost when compared with the other designs.",

author = "Tsai, {Min C.} and Tian-Sheuan Chang",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2006.342056",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "586--589",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "null ; Conference date: 04-12-2006 Through 06-12-2006",

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Tsai, MC & Chang, T-S 2006, High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145461, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 586-589, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 4/12/06. https://doi.org/10.1109/APCCAS.2006.342056

High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding. / Tsai, Min C.; Chang, Tian-Sheuan.

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 586-589 4145461 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a high-performance VLSI architecture for context adaptive variable length coding (CAVLC) used in the MPEG-4 AVC/H.264 video coding. Instead of only the coarse-grained 8×8 zero block skipping in the previous design, the proposed design implements the fine-grained zero skipping at the 4×4 block level and the individual coefficient level. The implementation with 0.18um CMOS process just needs average 6.88 cycles for one block coding and costs 11.9K gates when working at 100 MHz. This design saves more than half of cycle count and 48% of area cost when compared with the other designs.

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