High-Performance Bipolar Technology for Improved ECL Power Delay

J. Warnock, J. D. Cressler, K. A. Jenkins, C. Stanis, J. Y.C. Sun, D. D. Tang, E. Petrillo, C. K. Hu

Research output: Contribution to journalArticle

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Abstract

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. ECL ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ), an improvement of 17% from the nonbutted case. In addition, more conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date.

Original languageEnglish
Pages (from-to)315-317
Number of pages3
JournalIEEE Electron Device Letters
Volume12
Issue number6
DOIs
StatePublished - Jun 1991

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    Warnock, J., Cressler, J. D., Jenkins, K. A., Stanis, C., Sun, J. Y. C., Tang, D. D., Petrillo, E., & Hu, C. K. (1991). High-Performance Bipolar Technology for Improved ECL Power Delay. IEEE Electron Device Letters, 12(6), 315-317. https://doi.org/10.1109/55.82072