High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Hao I. Yang*, Yi Wei Lin, Mao Chih Hsia, Geng Cing Lin, Chi Shin Chang, Yin Nien Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan Chun Lien, Hung Yu Li, Kuen Di Lee, Wei Chiang Shih, Ya Ping Wu, Wen Ta Lee, Chih Chiang Hsu

*Corresponding author for this work

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.

Original languageEnglish
Pages1831-1834
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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