High performance 0.15 μm single gate Co salicide CMOS

T. Yoshitomi*, T. Ohguro, M. Saito, M. Ono, E. Morifuji, H. S. Momose, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations


A high performance 0.15 μm single gate Co salicide CMOS technology was developed by optimizing the fabrication conditions of pMOSFETs extension region. The gate delay of 19.8 psec was obtained with good suppression of short channel effect. At 0.12 μm gate length, 11-5 psec, the fastest tpd ever reported, was observed although the short channel effects were significant at this moment. These results suggest that high performance single gate CMOS in sub-0.15 μm region can be realized by further improving the extension conditions such as by using new doping techniques.

Original languageEnglish
Pages (from-to)34-35
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1996
EventProceedings of the 1996 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 11 Jun 199613 Jun 1996

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