High level simulator feasible for reliability analysis of VLSI circuits

Steve S. Chung*, Tian-Sheuan Chang, P. C. Hsu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A high level timing simulator has been developed with emphasis on design-for-reliability of VLSI circuits, in particular digital circuits. It features high speed performance which is at least 100× faster than SPICE for circuit simulation. The input is at the gate-level and so is more suitable for VLSI circuit analysis. A new reliability model is also incorporated in the simulator so that the simulator is feasible for reliability analysis of device or circuit degradation due to the hot carrier effect. Two typical examples for predicting the lifetime of a device or circuit in a VLSI environment will be demonstrated.

Original languageEnglish
Title of host publicationFourth Annual IEEE International ASIC Conference and Exhibit
PublisherPubl by IEEE
ISBN (Print)0780301013
DOIs
StatePublished - 1 Dec 1991
EventProceedings Fourth Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: 23 Sep 199127 Sep 1991

Publication series

NameFourth Annual IEEE International ASIC Conference and Exhibit

Conference

ConferenceProceedings Fourth Annual IEEE International ASIC Conference and Exhibit
CityRochester, NY, USA
Period23/09/9127/09/91

Fingerprint Dive into the research topics of 'High level simulator feasible for reliability analysis of VLSI circuits'. Together they form a unique fingerprint.

Cite this