High-K gate dielectrics

Hei Wong*, Kenji Shiraishi, Kuniyuki Kakushima, Hiroshi Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapter

2 Scopus citations

Abstract

To maintain a proper control of the drain current flow in nanoscale CMOS devices, the thickness of silicon dioxide which has been used as the gate dielectric material for over four decades is now pushed into its technological limit of about 1 nmand theoretical limit of 0.7 nm. Further device downsizing would require even thinner gate dielectric films. This stringent requirement can only be achieved by using a high-dielectric constant (high-k) material. High-k gate dielectric together with metal gate electrode has been recognized as an effective technological option to boost the performance of present integrated circuit technology. However, there are still a lot of issues need to be solved in order to incorporate this new material into the existing CMOS technology. This chapter reviews the development of high-k gate dielectric materials for nanoscale CMOS device applications.We shall focus on the issues related to the electrical properties and the reliability of high-k materials used as the MOS gate dielectrics.

Original languageEnglish
Title of host publicationElectronic Device Architectures for the Nano-CMOS Era
Subtitle of host publicationFrom Ultimate CMOS Scaling to Beyond CMOS Devices
PublisherPan Stanford Publishing Pte. Ltd.
Pages105-140
Number of pages36
ISBN (Print)9789814241281
DOIs
StatePublished - 1 Oct 2008

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    Wong, H., Shiraishi, K., Kakushima, K., & Iwai, H. (2008). High-K gate dielectrics. In Electronic Device Architectures for the Nano-CMOS Era: From Ultimate CMOS Scaling to Beyond CMOS Devices (pp. 105-140). Pan Stanford Publishing Pte. Ltd.. https://doi.org/10.4032/9789814241298