The use of high-k (HiK) dielectrics has enabled further downsizing of CMOS devices, towards the nanoscale range. However, the gate oxide scaling, in the sense of equivalent oxide thickness (EOT), has already lost its momentum. In the subnanometer EOT, or for a couple nanometer physical thickness, most HiK materials fail to maintain their superior electrical properties. In addition, the related interface layers (HiK/silicon substrate and HiK/metal gate) are not directly scalable. They limit the smallest achievable EOT and govern some of the device properties such as channel mobility, subthreshold conduction, etc. This work highlights the major challenges coming across with the EOT scaling in the subnanometer range. Some future perspectives such as the use of alternative gate electrode materials and crystalline HiK for interface control will also be discussed.