High-gain monolithic 3D CMOS inverter using layered semiconductors

Angada B. Sachid, Sujay B. Desai, Ali Javey, Chen-Ming Hu

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.

Original languageEnglish
Article number222101
JournalApplied Physics Letters
Volume111
Issue number22
DOIs
StatePublished - 27 Nov 2017

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