High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology

R. V. Joshi*, Wei Hwang, C. T. Chuang

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

Circuit techniques for self-resetting CMOS (SRCMOS) designs in partially depleted (PD) silicon on insulator (SOI) technology in which pulsewidth alignment and control were difficult due to the hysteresis were presented. The input pulses were rendered within the specifications with the help of static and dynamic input isolation circuits provided at the interface of the macro boundary in asynchronous CMOS design. The robustness of the circuit was demonstrated over wide ranges of temperature.

Original languageEnglish
Pages140-141
Number of pages2
StatePublished - 1 Dec 2000

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