Circuit techniques for self-resetting CMOS (SRCMOS) designs in partially depleted (PD) silicon on insulator (SOI) technology in which pulsewidth alignment and control were difficult due to the hysteresis were presented. The input pulses were rendered within the specifications with the help of static and dynamic input isolation circuits provided at the interface of the macro boundary in asynchronous CMOS design. The robustness of the circuit was demonstrated over wide ranges of temperature.
|Number of pages||2|
|State||Published - 1 Dec 2000|