High efficiency data access system architecture for deblocking filter supporting multiple video coding standards

Cheng An Chien*, Guo An Jian, Hsiu Cheng Chang, Kuan Hung Chen, Jiun-In  Guo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


This paper presents an efficient VLSI architecture of in-loop deblocking filter (ILF) with high efficiency data access system for supporting multiple video coding standards including H.264 BP/MP/HP, SVC, MVC, AVS, and VC-1. Advanced standards, such as H.264 MP/HP, SVC, and MVC, adopt Macro Block Adaptive Frame Field (MBAFF) to enhance coding efficiency which results in the performance bottleneck of deblocking filter due to complex data access requirement. This design challenge has not been discussed in previous works according to our best knowledge. Therefore, we develop a Prediction Data Management (PDM) to manage the input prediction data order of deblocking filter for different coding types (like frame/field) and multiple standards. We also design an extended output frame buffer module to solve the system bus architecture restriction (like 1K boundary and burst length) and achieve high efficiency data access by using MB-based scan order. By using these techniques, we can solve the data accessing design challenge and reduce 67% bus latency. After being implemented by using 90 nm CMOS technology, the proposed work can achieve real-time performance requirement of QFHD (3840Ã - 2160@30fps) when operated at 156MHz at the cost of 50.6K gates and 2.4K bytes local memory. The maximum operating frequency of the proposed design, i.e. 370MHz, is higher than the required real-time operating frequency so that voltage scaling may be adopted to reduce power consumption.

Original languageEnglish
Article number6227475
Pages (from-to)670-678
Number of pages9
JournalIEEE Transactions on Consumer Electronics
Issue number2
StatePublished - 16 Jul 2012


  • Deblocking filter
  • High efficiency
  • Multiple video standards

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