High-current failure model for VLSI interconnects under short-pulse stress conditions

Kaustav Banerjee*, Ajith Amerasekera, Nathan Cheung, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

56 Scopus citations

Abstract

Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this letter, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 μm CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.

Original languageEnglish
Pages (from-to)405-407
Number of pages3
JournalIEEE Electron Device Letters
Volume18
Issue number9
DOIs
StatePublished - 1 Sep 1997

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