Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a cycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing and processing the pre-decoded information in the cache. In the paper, the authors propose to use an Instruction Identifier to predict instruction length and store the instruction pointers as superscalar instruction group indicators. With this method, the difficulty of achieving a high instruction fetch degree (>3) can be overcome. Simulation results suggest that the Instruction Identifier with a 64-entry table is a good performance/cost choice. In the meantime, as the table size decreases, the prediction scheme becomes increasingly important. Moreover, simulation and circuit synthesis show that this design is feasible for high clock rate design.