High-aspect ratio through silicon via (TSV) technology

H. B. Chang; H. Y. Chen; P. C. Kuo; Chao-Hsin Chien; E. B. Liao; T. C. Lin; T. S. Wei; Y. C. Lin; Y. H. Chen; K. F. Yang; H. A. Teng; W. C. Tsai; Y. C. Tseng; S. Y. Chen; C. C. Hsieh; M. F. Chen; Y. H. Liu; T. J. Wu; Shang Y. Hou; W. C. Chiou; S. P. Jeng; C. H. Yu

doi:10.1109/VLSIT.2012.6242517

High-aspect ratio through silicon via (TSV) technology

H. B. Chang^*, H. Y. Chen, P. C. Kuo, Chao-Hsin Chien, E. B. Liao, T. C. Lin, T. S. Wei, Y. C. Lin, Y. H. Chen, K. F. Yang, H. A. Teng, W. C. Tsai, Y. C. Tseng, S. Y. Chen, C. C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, Shang Y. Hou, W. C. ChiouS. P. Jeng, C. H. Yu

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

20 Scopus citations

Abstract

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

Original language	English
Title of host publication	2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages	173-174
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2012.6242517
State	Published - 27 Sep 2012
Event	2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States Duration: 12 Jun 2012 → 14 Jun 2012

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2012 Symposium on VLSI Technology, VLSIT 2012
Country	United States
City	Honolulu, HI
Period	12/06/12 → 14/06/12

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Chang, H. B., Chen, H. Y., Kuo, P. C., Chien, C-H., Liao, E. B., Lin, T. C., Wei, T. S., Lin, Y. C., Chen, Y. H., Yang, K. F., Teng, H. A., Tsai, W. C., Tseng, Y. C., Chen, S. Y., Hsieh, C. C., Chen, M. F., Liu, Y. H., Wu, T. J., Hou, S. Y., ... Yu, C. H. (2012). High-aspect ratio through silicon via (TSV) technology. In 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers (pp. 173-174). [6242517] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2012.6242517

Chang, H. B. ; Chen, H. Y. ; Kuo, P. C. ; Chien, Chao-Hsin ; Liao, E. B. ; Lin, T. C. ; Wei, T. S. ; Lin, Y. C. ; Chen, Y. H. ; Yang, K. F. ; Teng, H. A. ; Tsai, W. C. ; Tseng, Y. C. ; Chen, S. Y. ; Hsieh, C. C. ; Chen, M. F. ; Liu, Y. H. ; Wu, T. J. ; Hou, Shang Y. ; Chiou, W. C. ; Jeng, S. P. ; Yu, C. H. / High-aspect ratio through silicon via (TSV) technology. 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. 2012. pp. 173-174 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{3a42fad219814146902652a239545886,

title = "High-aspect ratio through silicon via (TSV) technology",

abstract = "The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.",

author = "Chang, {H. B.} and Chen, {H. Y.} and Kuo, {P. C.} and Chao-Hsin Chien and Liao, {E. B.} and Lin, {T. C.} and Wei, {T. S.} and Lin, {Y. C.} and Chen, {Y. H.} and Yang, {K. F.} and Teng, {H. A.} and Tsai, {W. C.} and Tseng, {Y. C.} and Chen, {S. Y.} and Hsieh, {C. C.} and Chen, {M. F.} and Liu, {Y. H.} and Wu, {T. J.} and Hou, {Shang Y.} and Chiou, {W. C.} and Jeng, {S. P.} and Yu, {C. H.}",

year = "2012",

month = sep,

day = "27",

doi = "10.1109/VLSIT.2012.6242517",

language = "English",

isbn = "9781467308458",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "173--174",

booktitle = "2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers",

note = "null ; Conference date: 12-06-2012 Through 14-06-2012",

}

Chang, HB, Chen, HY, Kuo, PC, Chien, C-H, Liao, EB, Lin, TC, Wei, TS, Lin, YC, Chen, YH, Yang, KF, Teng, HA, Tsai, WC, Tseng, YC, Chen, SY, Hsieh, CC, Chen, MF, Liu, YH, Wu, TJ, Hou, SY, Chiou, WC, Jeng, SP & Yu, CH 2012, High-aspect ratio through silicon via (TSV) technology. in 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers., 6242517, Digest of Technical Papers - Symposium on VLSI Technology, pp. 173-174, 2012 Symposium on VLSI Technology, VLSIT 2012, Honolulu, HI, United States, 12/06/12. https://doi.org/10.1109/VLSIT.2012.6242517

High-aspect ratio through silicon via (TSV) technology. / Chang, H. B.; Chen, H. Y.; Kuo, P. C.; Chien, Chao-Hsin; Liao, E. B.; Lin, T. C.; Wei, T. S.; Lin, Y. C.; Chen, Y. H.; Yang, K. F.; Teng, H. A.; Tsai, W. C.; Tseng, Y. C.; Chen, S. Y.; Hsieh, C. C.; Chen, M. F.; Liu, Y. H.; Wu, T. J.; Hou, Shang Y.; Chiou, W. C.; Jeng, S. P.; Yu, C. H.

2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. 2012. p. 173-174 6242517 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High-aspect ratio through silicon via (TSV) technology

AU - Chang, H. B.

AU - Chen, H. Y.

AU - Kuo, P. C.

AU - Chien, Chao-Hsin

AU - Liao, E. B.

AU - Lin, T. C.

AU - Wei, T. S.

AU - Lin, Y. C.

AU - Chen, Y. H.

AU - Yang, K. F.

AU - Teng, H. A.

AU - Tsai, W. C.

AU - Tseng, Y. C.

AU - Chen, S. Y.

AU - Hsieh, C. C.

AU - Chen, M. F.

AU - Liu, Y. H.

AU - Wu, T. J.

AU - Hou, Shang Y.

AU - Chiou, W. C.

AU - Jeng, S. P.

AU - Yu, C. H.

PY - 2012/9/27

Y1 - 2012/9/27

N2 - The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

AB - The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

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U2 - 10.1109/VLSIT.2012.6242517

DO - 10.1109/VLSIT.2012.6242517

M3 - Conference contribution

AN - SCOPUS:84866531869

SN - 9781467308458

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 173

EP - 174

BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers

Y2 - 12 June 2012 through 14 June 2012

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