High-aspect ratio through silicon via (TSV) technology

H. B. Chang*, H. Y. Chen, P. C. Kuo, Chao-Hsin Chien, E. B. Liao, T. C. Lin, T. S. Wei, Y. C. Lin, Y. H. Chen, K. F. Yang, H. A. Teng, W. C. Tsai, Y. C. Tseng, S. Y. Chen, C. C. Hsieh, M. F. Chen, Y. H. Liu, T. J. Wu, Shang Y. Hou, W. C. ChiouS. P. Jeng, C. H. Yu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations

Abstract

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages173-174
Number of pages2
DOIs
StatePublished - 27 Sep 2012
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: 12 Jun 201214 Jun 2012

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2012 Symposium on VLSI Technology, VLSIT 2012
CountryUnited States
CityHonolulu, HI
Period12/06/1214/06/12

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