High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory

Yun Yan Chung, Chao Ching Cheng, Yu Che Chou, Wei Chen Chueh, Wan Hsuan Chung, Zhihao Yu, Terry Yi Tse Hung, Lin Yun Huang, Shin Yuan Wang, Li Cheng Teng, Wen Ho Chang, Lain Jong Li, Chao Hsin Chien*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.

Original languageEnglish
Article number9206053
Pages (from-to)1649-1652
Number of pages4
JournalIeee Electron Device Letters
Volume41
Issue number11
DOIs
StatePublished - Nov 2020

Keywords

  • Charge-trap memory
  • contralateral-gated
  • MoS
  • neural networks
  • nonvolatile
  • transition metal dichalcogenide (TMD)

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