High-κ gate dielectrics for Ge CMOS and related memory devices

Albert Chin*, P. C. Chen, C. H. Cheng, Y. H. Wu, X. Y. Liu, J. F. Kang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To reach future low power operation at ≤0.5 V, high mobility InGaAs nMOS and Ge pMOS were proposed at sub-14 nm nodes. However, the integration of InGaAs on Si faces difficult challenges of the large 8% lattice-mismatch, high dislocation densities, and antiphase domain boundaries. Although the defect-free Ge-on-Insulator (GOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI) on Si, and selective GOI were reported by us, it is still different to reach IIIVOI and GOI side-by-side for high mobility InGaAs-Ge CMOS. On the other hand, the Ge has both higher electron and hole mobility than Si for all Ge CMOS. The GOI pMOS on Si has achieved 2.6 times higher hole mobility than universal SiO 2 /Si value at a medium effective field (E eff ) of 0.5 MV/cm and a small equivalent-oxidethickness (EOT) of 1.4 nm. Although the GeO 2 /Ge nMOS reported high peak mobility at small E eff , fast mobility degradation with increasing E eff and decreasing EOT were found.

Original languageEnglish
Title of host publication2012 International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Proceedings
Pages64-65
Number of pages2
DOIs
StatePublished - 30 Jul 2012
Event6th International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Berkeley, CA, United States
Duration: 4 Jun 20126 Jun 2012

Publication series

Name2012 International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Proceedings

Conference

Conference6th International Silicon-Germanium Technology and Device Meeting, ISTDM 2012
CountryUnited States
CityBerkeley, CA
Period4/06/126/06/12

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