High-κ dielectric scaling for nano-CMOS technology

Hei Wong*, Takamasa Kawanago, Kuniyuki Kakushima, Hiroshi Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

The thinning of the gate dielectric film has been one of the most critical measures for maintaining continuous downsizing of CMOS devices, and the gate dielectric thickness was the first physical quantity to be scaled down to the atomic scale. For the MOS devices with gate length in the decananometer range, the only way to maintain the continuous gate dielectric scaling is to use high-κ materials and to characterize the dielectric film thickness in terms of equivalent oxide thickness (EOT) instead of physical thickness. Subnanometer EOT gate dielectric has already been in use in recent technology nodes. However, further scaling of the 126gate dielectric film to the deep subnanometer range has come across many challenges in the fabrication process, material stability, interface thickness control, and device reliability as well. This chapter discusses various concerns regarding the process, material, and device characteristics of the-state-of-the-art subnanometer high-κ gate dielectrics. Some potential options for future high-κ processes are also highlighted.

Original languageEnglish
Title of host publicationIntegrated Nanodevice and Nanosystem Fabrication
Subtitle of host publicationBreakthroughs and Alternatives
PublisherPan Stanford Publishing Pte. Ltd.
Pages125-179
Number of pages55
ISBN (Electronic)9781351721783
ISBN (Print)9789814774222
DOIs
StatePublished - 1 Jan 2017

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    Wong, H., Kawanago, T., Kakushima, K., & Iwai, H. (2017). High-κ dielectric scaling for nano-CMOS technology. In Integrated Nanodevice and Nanosystem Fabrication: Breakthroughs and Alternatives (pp. 125-179). Pan Stanford Publishing Pte. Ltd.. https://doi.org/10.1201/9781315181257