Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization

Wei Hsun Liao, Chang Tzu Lin, Sheng Hsin Fang, Chien Chia Huang, Hung-Ming Chen, Ding Ming Kwai, Yung Fa Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.

Original languageEnglish
Title of host publication2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages549-553
Number of pages5
ISBN (Electronic)9781509015580
DOIs
StatePublished - 16 Feb 2017
Event22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan
Duration: 16 Jan 201719 Jan 2017

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
CountryJapan
CityChiba
Period16/01/1719/01/17

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  • Cite this

    Liao, W. H., Lin, C. T., Fang, S. H., Huang, C. C., Chen, H-M., Kwai, D. M., & Chou, Y. F. (2017). Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 (pp. 549-553). [7858381] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2017.7858381