Harvest rate of reconfigurable pipelines

Weiping Shi*, Ming-Feng Chang, W. Kent Fuchs

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, we prove when n = Θ(m), the harvest rate is between 34% and 72%.

Original languageEnglish
Pages (from-to)1200-1203
Number of pages4
JournalIEEE Transactions on Computers
Issue number10
StatePublished - 1 Dec 1996


  • Defect tolerance
  • Harvest rate
  • Percolation
  • Pipelines
  • Random graphs
  • Reconfigurable arrays
  • Yield

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