Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

Lan-Da Van, Tsung Che Lu, Tzyy Ping Jung, Jo Fu Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.

Original languageEnglish
Title of host publication2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1438-1442
Number of pages5
ISBN (Electronic)9781479981311
DOIs
StatePublished - 1 May 2019
Event44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Brighton, United Kingdom
Duration: 12 May 201917 May 2019

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume2019-May
ISSN (Print)1520-6149

Conference

Conference44th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019
CountryUnited Kingdom
CityBrighton
Period12/05/1917/05/19

Keywords

  • and hardware implementation
  • Blind signal separation
  • component/channel switch
  • EEG
  • fast independent component analysis (FastICA)

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