Hardware-efficient DFT designs with cyclic convolution and subexpression sharing

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Abstract

This paper presents a hardware efficient design for the discrete Fourier transform (DFT). The proposed design not only applies the constant property, but also exploits the numerical property of the transform coefficients. DFT is first formulated as cyclic convolution form to make each DFT output sample computations have the same computation kernels. Then, by exploring the symmetries of DFT coefficients, the word-level hardware sharing can be applied, in which two times the throughput is obtained. Finally, bit-level common subexpression sharing can be efficiently applied to implement the complex constant multiplications by using only shift operations and additions. Though the three techniques have been proposed separately for transform, this paper integrates the above techniques and obtains additive improvements. The I/O channels in our design are limited to the two extreme ends of the architecture that results in low I/O bandwidth. Compared with the previous memory-based design, the presented approach can save 80% of gate area with two-times faster throughput for length N = 61. The presented approach can also be applied to power-of-two length DFT. Similar efficient designs can be obtained for other transforms like DCT by applying the proposed approach.

Original languageEnglish
Pages (from-to)886-892
Number of pages7
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume47
Issue number9
DOIs
StatePublished - 1 Sep 2000

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