Hardware-assisted syntax decoding model for software AVC/H.264 decoders

Ming Ju Wu*, Yi Tseng Chen, Chun-Jen Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG Reconfigurable Video Coding (RVC) Framework. A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2).

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1233-1236
Number of pages4
DOIs
StatePublished - 26 Oct 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 24 May 200927 May 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period24/05/0927/05/09

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