Gridless wire ordering, sizing and spacing with critical area minimization

Yu Wei Lee*, Yen Hung Lin, Yih-Lang Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Designs for yield (DFY) problems have received increasing attention. Of particular concern in DFY problems is how to formulate and reduce a critical area for random defects. Arranging interconnections is recognized as an effective means of improving the sensitivity towards random defects. Previous works have demonstrated that random defects significantly influence interconnections and the effectiveness of layer assignment and track routing to enhance routing quality and performance. This work proposes a random defect aware layer assignment and gridless track routing (RAAT) to eliminate the effect of random defects. Gridless track routing comprises wire ordering, wire sizing and spacing in this work. Exposure ratio metric is proposed to assign each iroute to a specific layer efficiently. RAAT utilizes min-cut partitioning, a conventionally adopted method for placement and floorplanning, to place interconnections. Slicing tree-based structure improves the efficiency of wire ordering in lowering overlapped length between adjacent partitions. Finally, a second-order cone programming refined by considering an extra random-defect effect determines the position and width of each iroute. Experimental results demonstrate the necessity of the integration of layer assignment and track routing. Results further demonstrate the effectiveness of the gridless track routing methods proposed by RAAT. In addition to finishing each case more rapidly with higher completion rate than previous works do, RAAT reduces up to 20% of the number of failures in the Monte Carlo simulation as compared to previous works.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages646-653
Number of pages8
DOIs
StatePublished - 22 Jun 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: 14 Mar 201116 Mar 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Conference

Conference12th International Symposium on Quality Electronic Design, ISQED 2011
CountryUnited States
CitySanta Clara, CA
Period14/03/1116/03/11

Keywords

  • Design for yield
  • gridless track routing
  • layer assignment
  • random defects

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  • Cite this

    Lee, Y. W., Lin, Y. H., & Li, Y-L. (2011). Gridless wire ordering, sizing and spacing with critical area minimization. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 646-653). [5770797] (Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011). https://doi.org/10.1109/ISQED.2011.5770797