We propose a novel graphic method to enable the analysis of the field-effect transistor (FET) threshold voltage variation Delta V-th due to random telegraph signals in a percolative channel. First, through technology computer-aided design simulation with no percolation, both a minimum Delta V-th and a critical curve in a m(loc) - sigma(loc) plot are produced. The former constitutes a statistical distribution far away from the conventional log-normal one. In the latter, m(loc) and sigma(loc) are the mean and the standard deviation, respectively, of a well-known normal variable in Mueller-Schulz's percolation theory. The critical m(loc) - sigma(loc) curve divides the plot into the allowed region and the forbidden region and will go down with increasing gate size. Then, Delta V-th contours in the allowed region are graphically created. While applying to existing experimental Delta V-th statistical distributions of SiON- and high-k metal gate (HKMG)-scaled FETs, resulting paired m(loc) and sigma(loc) at high Delta V-th remain intact, regardless of gate size or gate stack type. This means that the underlying percolation patterns resemble each other, due to the same manufacturing process used. However, if these paired m(loc) and sigma(loc) fall in the forbidden region, it is the critical m(loc) - sigma(loc) curve dominating. Application to bias and temperature instability statistical data in literature is straightforwardly well done.
- Bias and temperature instability (BTI); field-effect transistors (FETs); fluctuations; percolation; random telegraph signals (RTSs); technology computer-aided design (TCAD); trap
- MOSFETS; NOISE; MODEL