Grain boundary trap-induced current transient in a 3-D NAND flash cell string

Wei Liang Lin*, Wen Jer Tsai, C. C. Cheng, S. H. Ku, Lenvis Liu, S. W. Hwang, Tao Cheng Lu, Kuang Chao Chen, Tseung-Yuen Tseng, Chih Yuan Lu

*Corresponding author for this work

Research output: Contribution to journalArticle

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Abstract

Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 μs or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in 'pseudo' charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.

Original languageEnglish
Article number8666060
Pages (from-to)1734-1740
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume66
Issue number4
DOIs
StatePublished - 1 Apr 2019

Keywords

  • 3-D NAND flash
  • cell current/threshold voltage instability
  • gate-all-around (GAA)
  • grain boundary trap (GBT)
  • nonvolatile memory
  • polycrystalline silicon channel
  • program verify (PV)
  • transient
  • trapping/detrapping

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    Lin, W. L., Tsai, W. J., Cheng, C. C., Ku, S. H., Liu, L., Hwang, S. W., Lu, T. C., Chen, K. C., Tseng, T-Y., & Lu, C. Y. (2019). Grain boundary trap-induced current transient in a 3-D NAND flash cell string. IEEE Transactions on Electron Devices, 66(4), 1734-1740. [8666060]. https://doi.org/10.1109/TED.2019.2900736