In this paper, we explore the dependence of electrical characteristics on grain boundary position and size in 90 nm polysilicon thin film transistors (Poly-Si TFTs). To account for the grain boundary effect in sub-100 nm square-shaped-surrounding-gate (i.e., gate-all-around, GAA) Poly-Si TFTs, a three-dimensional (3D) quantum correction transport model is solved together with grain trap model computationally. For the 90 nm GAA Poly-Si TFT, effects of boundary position and size of a single grain on the intrinsic performance are stronger than that of a submicron GAA Poly-Si TFT. With the same grain boundary position and size, the 90 nm GAA Poly-Si TFTs suffer more serious threshold voltage variation and performance degradation. Grain boundary locating at the drain side leads to large characteristic variation. Effective reduction of grain size can alleviate short channel effect in 90 nm GAA Poly-Si TFTs.