Grain boundary effect in sub-100 nm surrounding-gate polysilicon thin film transistors

Yiming Li*, Bo Shian Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we explore the dependence of electrical characteristics on grain boundary position and size in 90 nm polysilicon thin film transistors (Poly-Si TFTs). To account for the grain boundary effect in sub-100 nm square-shaped-surrounding-gate (i.e., gate-all-around, GAA) Poly-Si TFTs, a three-dimensional (3D) quantum correction transport model is solved together with grain trap model computationally. For the 90 nm GAA Poly-Si TFT, effects of boundary position and size of a single grain on the intrinsic performance are stronger than that of a submicron GAA Poly-Si TFT. With the same grain boundary position and size, the 90 nm GAA Poly-Si TFTs suffer more serious threshold voltage variation and performance degradation. Grain boundary locating at the drain side leads to large characteristic variation. Effective reduction of grain size can alleviate short channel effect in 90 nm GAA Poly-Si TFTs.

Original languageEnglish
Title of host publication2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
Pages504-507
Number of pages4
StatePublished - 2006
Event2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006 - Cincinnati, OH, United States
Duration: 17 Jun 200620 Jun 2006

Publication series

Name2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
Volume2

Conference

Conference2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
CountryUnited States
CityCincinnati, OH
Period17/06/0620/06/06

Keywords

  • 3D modeling and simulation
  • Grain boundary
  • Grain size
  • Polysilicon TFTs
  • Square-shaped gate
  • Sub-100 nm
  • Surrounding gate
  • Trap

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