Grain boundary assisted degradation and breakdown study in cerium oxide gate dielectric using scanning tunneling microscopy

K. Shubhakar*, K. L. Pey, S. S. Kushvaha, S. J. O'Shea, N. Raghavan, M. Bosman, M. Kouda, K. Kakushima, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalArticle

26 Scopus citations

Abstract

The presence of grain boundaries (GBs) in polycrystalline high- κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2) -based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown.

Original languageEnglish
Article number072902
JournalApplied Physics Letters
Volume98
Issue number7
DOIs
StatePublished - 14 Feb 2011

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