Good 150 °C retention and fast erase characteristics in charge-trap-engineered memory having a scaled Si 3 N 4 Layer

S. H. Lin, Albert Chin, F. S. Yeh, S. P. McAlister

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

We report a new charge-trap-engineered flash non-volatile memory that has combined 5nm Si 3 N 4 and 0.9nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150°C under a 100μs and ±16V P/E, this device showed good device integrity of a 5.6V initial δV th window and 3.8V 10-year extrapolated retention window. These data are better than the 3.3V initial δV th and 1.7V 10-year data for a similar structure not having the extra HfON layer.

Original languageEnglish
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 15 Dec 200817 Dec 2008

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2008 IEEE International Electron Devices Meeting, IEDM 2008
CountryUnited States
CitySan Francisco, CA
Period15/12/0817/12/08

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