Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC

Fang Ting Chou, Chung-Chih Hung

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions at output, which is < 1 pVs. This brief utilizes a layout structure to improve the spurious-free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18-μm CMOS technology and consumes 20.7 mW at 400 MS/s.

Original languageEnglish
Article number7360216
Pages (from-to)2407-2411
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number6
DOIs
StatePublished - 1 Jun 2016

Keywords

  • Binary weighted
  • current switch
  • digital-to-analog converter (DAC)
  • dynamic capacitance
  • Glitch energy

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