Line edge roughness (LER) and via-line misalignment strongly impact the time-dependent breakdown of the low-k dielectrics used in nanometer IC technologies. In this paper, we investigate, theoretically and experimentally, the impact of the variability of geometry on breakdown. By considering the statistical distribution of thickness between adjacent conductors exhibiting LER, we show that the breakdown location is a function of voltage and occurs at the minimum dielectric thickness at high voltage, but moves to the median thickness at the low voltages. Using these concepts, we show that LER modifies the functional form of failure distributions, and leads to a systematic change in the Weibull β with voltage. Accurate reliability analysis requires new reliability extrapolation methodologies to account for these effects. We show that the minimum dielectric thickness present on a test structure or on a circuit is readily determined from routine measurements of dielectric thickness between metal lines. We verify theoretical predictions using measurements of failure distributions of both via and line test structures. Finally, we have shown that LER can significantly modify the apparent field dependence of the failure time, leading to ambiguity in the interpretation of the experimentally determined field dependence.
|Number of pages||10|
|Journal||IEEE Transactions on Device and Materials Reliability|
|State||Published - 1 Sep 2010|
- Cu/low-k interconnect reliability
- line edge roughness (LER)
- time-dependent dielectric breakdown (TDDB)