A new general experimental method for timing macromodel parameter extraction is proposed. Based on the general timing models developed and the measured timing data of CMOS inverters, the critical field exponent U//E//X//P of carrier mobilities in transient operation, the optimal gate/source voltage and pn-junction voltage, and the capacitances associated with a logic gate are extracted by using the proposed method. It is shown that the extracted value of U//E//X//P is twice the conventional value owing to the integration effect on the drain currents in delay calculations. The optimal linearization gate/source voltage is about 0. 7 V//D//D, whereas the pn-junction voltage is approximately V//D//D/2. By using the extracted timing parameters, the accuracy of the timing macromodels developed is improved and experimentally verified. The possibility of accuracy improvement and experimental verification makes the method helpful in developing efficient timing macromodels for digital VLSI.
|Number of pages||9|
|Journal||IEE Proceedings I: Solid State and Electron Devices|
|State||Published - 1 Jan 1988|