Ge/IIIV fin field-effect transistor common gate process and numerical simulations

Bo Yuan Chen, Jiann Lin Chen, Chun Lin Chu*, Guang Li Luo, Shyong Lee, Edward Yi Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

Original languageEnglish
Article number024501
JournalJournal of Micro/ Nanolithography, MEMS, and MOEMS
Volume16
Issue number2
DOIs
StatePublished - 1 Apr 2017

Keywords

  • atomic layer deposition
  • computational fluid dynamics
  • numerical simulation
  • transistors

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