Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

C. J. Su, T. C. Hong, Y. C. Tsou, F. J. Hou, P. J. Sung, M. S. Yeh, C. C. Wan, K. H. Kao, Y. T. Tang, C. H. Chiu, C. J. Wang, S. T. Chung, T. Y. You, Y. C. Huang, C. T. Wu, K. L. Lin, G. L. Luo, K. P. Huang, Y. J. Lee, Tien-Sheng ChaoW. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

Original languageEnglish
Title of host publication2017 IEEE International Electron Devices Meeting, IEDM 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15.4.1-15.4.4
ISBN (Electronic)9781538635599
DOIs
StatePublished - 23 Jan 2018
Event63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
Duration: 2 Dec 20176 Dec 2017

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference63rd IEEE International Electron Devices Meeting, IEDM 2017
CountryUnited States
CitySan Francisco
Period2/12/176/12/17

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