Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Zhen Ying Hsieh*, Mu Chun Wang, Shuang Yuan Chen, Chih Chen, Heng Sheng Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, VG = VD. The gate-to-drain capacitance, CGD - VG, with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of CGD - VG with different frequencies was precisely studied.

Original languageEnglish
Article number253503
JournalApplied Physics Letters
Volume95
Issue number25
DOIs
StatePublished - 1 Dec 2009

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